IISc Bangalore is looking for a VLSI Design intern.
The selected intern(s) will work on finding out the processor time required for logic simulation of standard benchmark circuits. The intern needs to first design some benchmark circuits using Verilog. Then the processor time required for the logic simulation of those Verilog source codes has to be recorded.
Who can apply: Candidates with good knowledge of Verilog and well understanding of microprocessor can apply for this internship. You should be proficient in Verilog programming (Xilinx ISE).
Location: Bangalore. Due to accommodation problem, they will prefer applicants from Bangalore.
Duration: 2 months.
Number of Internships: 1
Stipend: Rs. 10,000 per month.
For more details on this VLSI internship, visit our content partner’s website and apply there itself.
The last date to apply for this internship is September 28, 2015.
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